Conference Highlights

SOCC 2006 will offer three days of technical papers and a full day of technical workshops.
Please watch this site for updates on distinguished speakers and the technical program.
While we are finalizing the program for 2006, you may want to take a look at our previous conferences.

Distinguished Speakers: 
(click on name or scroll down page for more information)

SOCC 2006 -  Austin, TX

Keynote:

Gene Frantz

Principal Fellow, Texas Instruments
“How the Shrinking System is creating an Expanding Market”

Plenary:

Jan Rabaey

Donald O. Pederson Distinguished Professor,
University of California at Berkeley
“Curing the ailments of nanometer CMOS through self-healing and resiliency”

Plenary:

Jim Kahle

IBM Fellow and Director of Technology, STI Design Center for Cell Technology, IBM Corporation

Luncheon:

Dean Cubley

Director and Chairman, ERF Wireless
Director, Eagle Broadband Inc.
“The Wild West Days of NASA”

Panel Discussion:

Like every year, SOCC 2006 will feature a panel discussion on a hot controversial topic in the SoC area.

Corporate Sponsors and Exhibitors:

Corporate sponsors of our conference may be present with tabletop displays. For more information on corporate sponsorship, please see our Sponsors page

Tutorial Workshops:

Like in our previous conferences, there will be several half-day tutorials on Sunday.

Special Section in IEEE TVLSI:

The April/May 2007 issue of IEEE Transactions on VLSI Systems will feature a special section on System on Chip Integration. The special section will also highlight selected work presented at SOCC 2006. See the TVLSI Call for Papers for more information on the submission process and deadlines.

 

Keynote Speaker

Gene Frantz
Principal Fellow,
Texas Instruments
”How the Shrinking System is creating an Expanding Market”

Gene Frantz is responsible for finding new opportunities and creating new businesses utilizing TI’s digital signal processing technology. Mr. Frantz has been with Texas Instruments for over thirty years, most of it in Digital Signal Processing.  He is a recognized leader in DSP technology both within TI and throughout the industry. Throughout his tenure at TI, he has been recognized by his colleagues as one who has his fingers on the pulse of future trends. His documentation of the relationship between power dissipation and performance is becoming broadly accepted as "Gene's Law." Mr. Frantz is also among industry experts widely quoted in the media due to his tremendous knowledge and visionary view of DSP solutions.

Mr. Frantz is a Fellow of the IEEE. He holds over 40 patents in the areas of memories, speech, consumer products and DSP. He has written more than 50 papers and articles and continually presents at universities and conferences worldwide. He holds a bachelor's degree in electrical engineering from the University of Central Florida, an MSEE from Southern Methodist University and an MBA from Texas Tech University.

Abstract: Integrated circuit technology has been responsible for shrinking the size of a system.  It has come from a box (or rack) to a PCB to a System In Package (SIP) to a System on a Chip (SOC). What may be less obvious is the expanding market opportunities that the “shrinking system” is creating.

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Plenary Speakers

Jan Rabaey
Donald O. Pederson Distinguished Professor,
Director of GigaScale Systems Research Center (GSRC)
University of California at Berkeley
“Curing the ailments of nanometer CMOS through self-healing and resiliency”

Jan Rabaey received  the EE and Ph.D degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium, respectively in 1978 and 1983. From 1983 till 1985, he was connected to the University of California, Berkeley as a Visiting Research Engineer. From 1985 till 1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He has been a visiting professor at the University of Pavia (Italy), Waseda University (Japan), Technical University Delft (Netherlands), Victoria Technical University and the University of New South Wales (Australia). He was the Associate Chair (EE) of the EECS Dept. at Berkeley from 1999 till 2002, and is currently the Scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the GigaScale Systems Research Center (GSRC).

Jan Rabaey authored or co-authored a wide range of papers in the area of signal  processing and design automation. He is the author of  “Digital Integrated Circuits: A Design Perspective”, a state-of-the art textbook on digital circuit design (Prentice Hall, ISBN 0-13-178609-1). He is also the editor/author of “Low Power Design Methodologies” and “Power Aware Design Methodologies”, two Kluwer Academic Publisher books that present an in-depth coverage on low-power design ranging from the technology up to the system level.  Most recently, he co-edited ”Ambient Intelligence”, a Springer Verlag book on the applications, technology and systems aspects of the Ambient Intelligence concept.

Prof. Rabaey received numerous scientific awards,  including the 1985 IEEE Transactions on Computer Aided Design Best Paper Award (Circuits and Systems Society), the 1989 Presidential Young Investigator award, and the 1994 Signal Processing Society Senior Award, and the 2002 ISSCC Jack Raper Award. In 1995, he became an IEEE Fellow. He is past chair of the VLSI Signal Processing Technical Committee of the Signal Processing Society and chaired the executive committee of the Design Automation Conference. He is serving on the Technical Advisory Board of a wide range of companies.

His current research interests include the conception and implementation of next-generation integrated wireless systems. This includes the analysis and optimization of communication algorithms and networking protocols, the study of low-energy implementation architectures and circuits, and the supporting design automation environments.

Abstract: With scaling approaches the lower reaches of the nanometer scale, a whole slew of ailments and potentially fatal injuries will make correct operation of complex SOCs over a longer period of time ever harder. While a lot can be accomplished with device and technology improvements, the burden will really lay on the shoulders of the circuit and architecture designer to cure these challenges. In this presentation, we will give an overview of a number of techniques that may potentially be of use in the creation of designs that are either self-healing, or that have enough resiliency built in to render them immune to these ailments. The presentation is built on results and ideas that are raised as a part of the Gigascale System Research Center (GSRC), a multi-university collaborative effort.

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Jim Kahle
IBM Fellow,
Director of Technology, STI Design Center for Cell Technology,
IBM Corporation

Jim Kahle is a renowned expert in the microprocessor industry, currently holding the position of IBM Fellow, and he is the Director of Technology for the Austin-based STI Design Center for Cell Technology, which is a partnership with IBM, Sony and Toshiba. Mr.Kahle has been working for IBM since the early 1980s on RISC-based microprocessors, and since then he has held numerous managerial and technical positions. His work started in physical design tools and is currently concentrated on RISC architecture. Mr. Kahle was a key designer for the RIOS I processor, which launched IBM into the RS/6000 line of workstations and servers. He was also one of the founding members of the Somerset Design Center, where he was the project manager for the PowerPC 603 and follow-on processors which led to the PowerPC G3. He was key to the definition of the PowerPC architecture and of the superscalar techniques used at IBM, and has been at the forefront of superscalar design and multiscalar and SMT microarchitectures. Mr. Kahle was the Chief Architect for the POWER4 core used in IBM servers and Apple's G5, and assists in PowerPC roadmap planning.

Jim Kahle has been involved in designs using the Power architecture since its conception. He combines broad processor knowledge with an ability to lead high performance teams and to drive deep client relationships in order to understand future system requirements, achieving breakthrough innovations in chip design. Jim Kahle holds about 160 patents in the area of processor architecture. He received his B.S. degree from Rice University in 1983.

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Luncheon Speaker

Dean Cubley
Director and Chairman, ERF Wireless
Director, Eagle Broadband Inc.
“The Wild West Days of NASA”

Dr. H. Dean Cubley has served as director and chairman of ERF Wireless since May 2004. Dr. Cubley has served as a director of Eagle Broadband Inc. (f/k/a Eagle Wireless International Inc.), since March of 1996; was chairman of the board from March 1996 to April 2004; chief executive officer from March 1996 to October 2003; and president from March 1996 until September 2001. Prior to that, Dr. Cubley served as vice-president of Eagle Telecom Inc. from 1993 to March 1996. From 1984 until 1993, Dr. Cubley was active in the telecommunications industry serving as a principal in numerous high-technology companies including Metrocast, Microlink, TI-IN and Paging Products International.

Dr. Cubley has over 40 years extensive experience in the telecommunications industry, serving as a principal in numerous high-technology companies including Metrocast, Microlink, TI-IN Network, and Paging Products International. From 1965 to 1984, Dr. Cubley worked for the NASA Manned Spacecraft Center as a senior engineer or manager on all Gemini, Apollo, and Shuttle programs.

Dr. Cubley was the antenna subsystems manager on all manned spacecraft programs for seven years during the Apollo Program with full project control for over $200 million worth of equipment for each Apollo flight. In addition, Dr. Cubley was the NASA project manager on the $500 million Apollo 17 Surface Electrical Properties Experiment which was searching for water on the surface of the moon in 1972.

During his career, Dr. Cubley has authored or co-authored over fifty publications. In addition, he is named on a total of 15 patents and pending patent applications. Dr. Cubley received a B.S. degree in electrical engineering from the University of Texas in 1964 and an M.S. degree from the University of Texas in 1965. In 1970 Dr. Cubley received his Ph.D. in electrical engineering from the University of Houston. Since 1977, Dr. Cubley has been actively engaged in the commercial telecommunications industry and has been instrumental in many of its technological advancements. He is an active member of the Institute of Electrical and Electronic Engineers (IEEE). Dr. Cubley has also been a founding partner in 23 new high-technology companies since his employment with NASA. Many of these companies have been acquired by larger companies and are currently operating in the telecommunications industry.

Abstract: This presentation will explore some of the early happenings at the Manned Spacecraft Center (Now the Johnson Space Center) from the viewpoint of one of the NASA engineers who spent the first twenty years of his career developing and managing development of Gemini, Apollo, Shuttle, and Space Station telecommunications technology.

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