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CONFERENCE-AT-A-GLANCE

Sunday, September 24 - Tutorial Workshops

Morning Workshops

Tutorial Track A

Tutorial Track B

8:00 a.m. -
10:00 a.m.

SA1
RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs
Martin Margala, University of Rochester

SB1
Design of Digital PLLs for Low Power Applications
Krishnasawamy Nagaraj, Texas Instruments Inc.

10:30 a.m. -
12:30 p.m.

SA2
High-performance energy-efficient memory circuit technologies for sub-45nm technologies
Amit Agarwal and Ram Krishnamurthy, Intel Corporation

SB2
Silicon Debug and DFT Tutorial for SOC IP Providers
Nikhil Dakwala, Stridge

Afternoon Workshops

 

 

2:00 p.m. -
5:00 p.m.

SA3
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities
Azad Naeemi and Muhannad Bakir, Georgia Institute of Technology

SB3
On-chip Distributed Communication - Architectures, Services and Design Methodologies
Tiberiu Seceleanu, University of Turku (UTU), Finland

Monday, September 25

Registration
7:00 a.m. -
5:00 p.m.

 

Plenary Session
8:15 a.m. -
11:30 a.m.

Opening Remarks:
   Ram Krishnamurthy, General Conference Chair
Technical Program Overview:
   Suhwan Kim, Technical Program Chair
Keynote Presentation:
   Gene Frantz, Principal Fellow, Texas Instruments, Inc.
Plenary Presentations:
   Prof. Jan Rabaey, Professor and Director of GigaScale Systems Research Center (GSRC), University of California at Berkeley
Jim Kahle, IBM Fellow, and Director of Technology, STI Design Center for Cell Technology, IBM Corporation

Lunch
11:30 a.m. -
1:00 p.m.

(on your own)

Technical Sessions
1:00 p.m. -
2:40 p.m.

Track A
MA2:
Analog Design for SoC

Track B
MB2:
DSP and Embedded Systems

3:00 p.m. -
4:40 p.m.

MA3:
RF Circuits and Systems

MB3:
Network and Reconfigurable Architectures

4:45 p.m. -
6:00 p.m.

POSTER SESSION and Conference Reception

Tuesday, September 26

Registration
7:30 a.m. -
5:00 p.m.

 

Technical Sessions
8:30 a.m. -
10:10 a.m.

Track A
TA1: Mixed-Signal Circuits and Systems

Track B
TB1: Industrial SoC Applications and Methods

10:30 a.m. -
11:45 a.m.

TA2: Low Power Design Techniques

TB2: System Level Design Methodology

Luncheon
11:45 a.m. -
1:15 p.m.

Guest speaker:
Dr. H. Dean Cubley, Chairman of Eagle RF, Inc.

Technical Sessions
1:40 p.m. -
3:20 p.m

Track A
TA3: Power Management Techniques

Track B
TB3: Design Tools for SoC

3:30 p.m. -
5:30 p.m.

Panel Discussion

6:00 p.m. -
8:00 p.m.

Special Workshops and Conference Reception
2010: Ubiquitous FPGAs
John B. Gallagher, Sr. Director, Outbound Marketing, Synplicity, Inc.

8:10 p.m. -
9:10 p.m.

Technical Program Committee and
Organizing Committee Members only Meeting

Wednesday, September 27

Registration
8:00 a.m. -
3:30 p.m.

 

Technical Sessions
8:30 a.m. -
10:10 a.m.

Track A
WA1: High Performance Digital Systems

Track B
WB1: Design for Testability, Manufacturability and Validation

10:30 a.m. -
11:45 a.m.

WA2: High Performance Digital Circuits

WB2: Wireline and Wireless Communications

Lunch
11:45 a.m. - 1:30 p.m.

(on your own)

Technical Sessions
1:30 p.m. -
3:10 p.m.

Track A
WA3: Signal Integrity and In-Chip Interconnections

Track B
WB3: Embedded Memories

3:10 p.m.

CONFERENCE ENDS